This invention relates to integrated circuits, and more particularly to integrated circuits including both rising edge-triggered circuits to a falling edge-triggered circuits.
Modern Integrated Circuits (IC) fabrication processes have reduced the size of transistors such that hundreds of millions of transistors can be inexpensively fabricated on a single semiconductor wafer, or xe2x80x9cchipxe2x80x9d. This capability has lead to an increased number of different functions performed on a single chip, giving rise to so-called System-On-a-Chip (SOC) devices. For example, a SOC device may include a micro controller (MCU), a digital signal processor (DSP), a reduced instruction set (RISC) processor, memory, and application specific logic circuitry combined on a single chip.
FIG. 1 is a flow diagram illustrating a simplified conventional process for designing and fabricating a SOC device 100. At the beginning of the design phase, a circuit designer typically selects an IC family that is defined, for example, by the fabrication process and chip size of the completed IC, along with any pre-defined arrangements of transistors and/or contact pads. The user then enters a logic design into a computer or workstation 110 using an input device 111. Computer 110 is loaded with a logic design entry software tool 113 that is typically linked to a design library 115 containing pre-defined circuit structures and design parameters associated with the selected IC family. Design library 115 also typically includes one or more pre-defined logic elements (often referred to as xe2x80x9cmacrosxe2x80x9d) that can be selected by the user during the logic design entry process. The user utilizes entry tool 113 to link these pre-defined logic elements with custom-designed logic elements (if any) to construct the logic design. Once the logic design is entered, place and route tools 117, also loaded on computer 110, are utilized to generate a place-and-route solution, which arranges the various interrelated portions of the logic design in an efficient two-dimensional spatial relationship that can be fabricated on a chip, and generates signal lines (interconnect wires) for passing signals between the interrelated portions. A layout tool 119 is then utilized to construct a three-dimensional representation of the actual circuit structures (e.g., regions of doped semiconductor, insulated regions, and metal lines) needed to implement the logic design. The three-dimensional representation is then used to generate a set of masks (step 120) that are then used to fabricate IC device 100 (step 130) using known fabrication techniques.
As the number of transistors and functions performed on each chip increases, the possibility of device failure due to fabrication errors also increases. Accordingly, IC manufacturers typically utilize one or more device testing methodologies to test each fabricated device 100 prior to being sold to an end user.
Design-For-Testability (DFT) is one type of standard methodology utilized to test modern ICs, such as SOC device 100, before sale to an end user. Referring to the lower portion of FIG. 1, according to conventional DFT methodology, SOC device 100 is mounted onto a test fixture 140 such that the terminals (contact pads) of SOC device 100 are connected via corresponding wires to a testing station 150. Testing station 150 (e.g., a computer or workstation) stores one or more DFT software tools 155 that are utilized during testing. One such test performed using DFT tools 155 is referred to as xe2x80x9cscan testxe2x80x9d, and includes shifting test data values into the device under test (step 142), causing the device under test to apply the test data to selected internal circuitry (step 144), and then shifting out the resulting test data (step 146). The resulting test data is then compared with expected result data to detect erroneous operation of the device under test. If the device under test passes all such testing, the device is then designated for sale to an end user. If the device fails this testing, it is typically discarded.
According to DFT methodology, test data values are serially shifted through a device under test using special (xe2x80x9cscanxe2x80x9d) flip-flops arranged to form xe2x80x9cscan pathsxe2x80x9d. The scan paths are determined during the design phase of IC production (i.e., steps 113 and 117, discussed above), and include several scan flip-flops connected in series.
FIG. 2 is a simplified circuit diagram showing an IC device 200 including scan flip-flops FF-1 and FF-2, along with combinational logic circuitry (CLC-1 and CLC-2) and additional circuitry discussed below. Flip-flop FF-1 has a scan input TI connected to receive a TEST value, a data input terminal D for receiving a DATA value, a clock terminal ( greater than ) connected to receive a clock signal CLK1, a data output terminal Q, and a scan enable terminal TE connected to receive a mode control signal MC. Similarly, flip-flop FF-2 has a scan input TI connected to the output terminal of flip-flop FF-1 by a scan path portion 201, a data input terminal D connected to receive a data value from combinational logic circuit CLC-1, a clock terminal ( greater than ), a data output terminal Q, and a scan enable terminal TE connected to receive mode control signal MC. Scan flip-flops FF-1 and FF-2 are constructed to operate in either a test mode or a normal operation mode, which is determined by mode control signal MC. During the test mode (e.g., mode control signal MC is asserted), each scan flip-flop FF-1 and FF-2 stores test data received from a preceding scan flip-flop in a scan path, thereby allowing test data values to be shifted along the scan path. For example, during the test mode, flip-flop FF-2 registers (stores) the test value passed from flip-flop FF-1 to its scan input terminal TI on scan path portion 201. Accordingly, the scan paths are utilized to pass test data into a device under test during test data input (step 142), and also to pass resulting test data out of the device during subsequent data output procedures (step 146). During normal operations (e.g., mode control signal MC is de-asserted), the scan flip-flops receive and store data values applied to data input terminals D. For example, during normal operation, flip-flop FF-2 registers data values generated by logic circuit CRC-1.
Conventional DFT tools (such as DFT tool 155; see FIG. 1) are typically purchased by an IC manufacturer from a company that specializes in producing such tools. For example, third-party DFT tools are commercially available from Mentor Graphics of Wilsonville, Oreg., and Synopsis Inc. of Sunnyvale, Calif. Such DFT tools facilitate testing by providing a test clock signal (e.g., CLK-1 in FIG. 2) supplied to the scan flip-flops (and other clocked elements) of a device under test during the test mode, and input/output circuitry for transmitting test data to and resulting data from the device under test. A problem associated with these currently available DFT tools arises when an IC manufacturer""s device includes both rising edge-triggered flip-flops and falling edge-triggered flip flops are utilized in an IC device. In particular, difficulties arise when a single clock signal is used to control both rising edge-triggered circuits and falling edge-triggered circuits during scan testing. For example, it both rising edge-triggered scan flip-flops and falling edge-triggered scan flip-flops are incorporated into the same scan path and driven by the same clock signal, then test data cannot be scanned (serially passed) using existing DFT tools. To circumvent this limitation of the DFT tools, IC manufacturers must devise test strategies that allow testing of the circuitry connected to both types of flip-flops.
Referring again to FIG. 2, simplified IC device 200 is modified according to one conventional method to facilitate testing both rising edge-triggered flip-flops (e.g., flip-flops FF-1 and FF-2) and falling edge-triggered flip-flops (e.g., FF-3) using conventional DFT tools. IC device 200 may include additional clocked circuits, such as high-level sensitive latch L-1 and low-level sensitive latch L-2.
To facilitate testing using a conventional DFT tool, IC device 200 incorporates two separate clock lines for transmitting two clock signals CLK-1 and CLK-2, respectively, that are supplied from an external source (i.e., tester 150 in FIG. 1) and applied to the rising edge-triggered circuits and falling edge-triggered circuits, respectively. Specifically, a first clock line 203 is utilized to transmit clock signal CLK-1 (through optional buffers B) to the clock terminals of flip-flops FF-1 and FF-2, and also to the clock terminal of latch L-1. Similarly, a second clock line 205 is utilized to transmit clock signal CLK-2 to the clock terminals of flip-flop FF-3 and latch L-2. Clock signals CLK-1 and CLK-2 are externally generated (e.g., by tester 150; see FIG. 1), and are applied to separate pins (contact pads) of IC device 200.
FIGS. 3(A) through 3(D) are timing diagrams depicting the clock signals CLK-1 and CLK-2 during normal and test modes in accordance with the conventional method. As shown in FIGS. 3(A) and 3(B), to facilitate testing using a conventional DFT tool, clock signal CLK-1 and clock signal CLK-2 are out of phase during the test mode, thereby causing the falling edge-triggered circuits (i.e., flip-flop FF-3 and latch L-2) to effectively operate as rising edge-triggered flip flops. During subsequent normal operation, as shown in FIGS. 3(C) and 3(D), clock signal CLK-1 and clock signal CLK-2 are in phase, thereby causing the falling edge-triggered circuits to operate normally.
There are several problems associated with the conventional method described above. For example, using two clock signals can produce relatively large clock skews and/or hold time problems due to the difficultly of generating separate clock signal lines during place and route. Also, additional cautions must be exercised during the design phase for signals that travel across clock domains (e.g., passing from a rising edge-triggered circuit to a falling edge-triggered circuit). Further, using two clock signals requires the use of a larger amount of chip space and/or slower chip operating speeds. Moreover, in comparison to single clock signal devices, the place and route process requires more routing space and additional clock tree circuits to support the multiple clock sources, which also contributes to the larger size and slower operating speeds of the device.
A second conventional approach utilizes a single clock signal, and provides clock signal inverting circuits that selectively invert the clock signal applied to selected flip-flops (e.g., all falling edge flip flops) of an IC device having both rising edge and falling edge flip-flops. The clock signal inverting circuits (e.g., multiplexers or exclusive-OR logic gates) are controlled by a mode control signal to pass either the clock signal or an inverted form of the clock signal to the selected flip-flops. Accordingly, the second conventional approach avoids the problems associated with utilizing two clock signals, but require a significant amount of chip space to support the multiple clock signal inverting circuits. Further, providing multiple clock signal inverting circuits greatly complicates clock skew management.
What is needed is a design methodology that facilitates the scan testing, using conventional DFT tools, of IC devices including both rising edge-triggered circuits to a falling edge-triggered circuits that minimizes clock signal skew and requires a minimum amount of chip area.
The present invention is directed to a method for fabricating IC devices including both rising edge-triggered circuits (e.g., flip-flops or latches) and falling edge-triggered circuits in which a clock signal line is selectively inverted by an on-chip clock signal inverting circuit during test modes. The normal (non-inverted) clock signal is routed, for example, to the rising edge-triggered flip-flops, and the selectively inverted clock signal is routed from the clock signal inverting circuit to, for example, the falling edge-triggered flip-flops. During the test mode, a test mode control signal causes the clock signal inverting circuit to invert the clock signal applied to the falling edge-triggered flip-flops, thereby causing the falling edge-triggered flip-flops to emulate rising edge-triggered flip-flops. By controlling the falling edge-triggered flip-flops using the on-chip clock signal inverting circuit, conventional DFT scan test tools can be utilized while minimizing the amount of clock signal skew and chip area needed to support both flip-flop types.
In accordance with a first specific embodiment of the present invention, the clock signal inverting circuit is implemented by a minimum number of logic gates (e.g., a two-input exclusive-OR (XOR) gate), thereby minimizing the amount of space required to generate the inverted clock signal during test modes. The mode control signal is routed to a first input terminal of the logic gate, and the clock signal is applied to a second input terminal of the logic gate. The output terminal of the logic gate is routed to, for example, the clock terminals of all falling edge-triggered flip-flops and latches of the integrated circuit.
In accordance with a second specific embodiment of the present invention, the clock signal inverting circuit is implemented by an inverter and a two-to-one multiplexer. The inverter is connected between the clock signal and a first data terminal of the multiplexer. The second data terminal of the multiplexer is connected to the (non-inverted) clock signal, and a select terminal of the multiplexer is connected to the mode control signal. During test operations, the mode control signal selects the inverted clock signal, which is passed to the falling edge-triggered circuits connected to the output terminal of the multiplexer. During normal operations, the mode control signal selects the (non-inverted) clock signal.
In accordance with a third embodiment of the present invention, a method for designing an integrated circuit including both rising edge and falling edge-triggered circuits includes arranging (placing) the integrated circuit components such that one type of clocked circuit (e.g., all falling edge-triggered circuits) are grouped together along with a clock signal inverting circuit, and routing a clock line from the clock signal inverting circuit to the clock terminals of each of the grouped circuits. The selected clocked circuits are grouped in a region of the integrated circuit area that minimizes clock skew between the clock signal inverting circuit and each selected clocked circuit. For example, the clock signal inverting circuit is placed such that a distance between the clock signal inverting circuit and each selected clocked circuit is minimized. Routing is performed such that a first wiring (clock signal) path is provided to each of the non-selected clocked circuits and to an input terminal of the clock signal inverting circuit. In addition, a second wiring path is provided for passing a mode control signal to a second input terminal of the clock signal inverting circuit, and a third wiring path is provided between an output terminal of the clock signal inverting circuit and the clock terminals of each of the selected clocked circuits. Accordingly, by grouping the selected clocked circuits to minimize clock skew (e.g., by placing the clock signal inverting circuit adjacent to the group), the selected clocked circuits can be controlled to emulate the non-selected clocked circuits during test mode operations, thereby allowing efficient DFT testing of integrated circuits including both rising and falling edge circuits using conventional DFT tools.